1. Field of the Invention
The present invention relates to a semiconductor device and method of manufacturing the same, and more particularly to a transistor device having one or more bipolar transistors and one or more MOS transistors integrated on one semiconductor substrate, and also to a method of manufacturing the same.
2. Description of the Prior Art
Recently, extensive attempts have been made to develop semiconductor devices having a so-called Bi-CMOS structure in which a bipolar transistor and complementary MOS transistors (CMOS transistors) integrated on one semiconductor substrate. Hereinafter, such a semiconductor device having a Bi-CMOS structure is often referred to as merely "Bi-CMOS".
FIG. 27 shows a conventional Bi-CMOS. This Bi-CMOS comprises: a P-silicon substrate 1 having an N.sup.+ -buried region 2 formed on its surface; an N-epitaxial layer 4 formed on the P-silicon substrate 1; a field oxide 6 formed adjacent the top surface of the N-epitaxial layer 4 and in an isolation region of a P.sup.+ -buried region 3 formed in the N-epitaxial layer 4 below the field oxide 6 in such a manner that it surrounds a region formed where the field oxide 6 is not formed (hereinafter, such a region is referred to as "an active region"), and reaches the substrate 1; a vertical bipolar transistor VBT formed in a portion of the active region within the N-epitaxial layer 4; two MOS transistors MT formed in the other portion of the field oxide region within the N-epitaxial layer 4; and an insulating layer 14 formed so as to cover the bipolar transistor VBT, the MOS transistors MT and the field oxide 6.
The vertical bipolar transistor VBT has a P-base region 7 formed within the N-epitaxial layer 4, an N-emitter region 9 within the P-base region 7, a gate oxide 8 formed on the emitter region 9, an emitter diffusion window 15 formed in a predetermined portion of the gate oxide 8, and an emitter electrode 11 formed on the gate oxide 8 for contact with the N-emitter region 9 through the emitter diffusion window 15.
One of the MOS transistors MT is an N-type MOS transistor having a P-well region 5 formed in the N-epitaxial layer 4, a gate oxide 8 formed on the P-well region 5, a gate electrode 10 formed on the gate oxide 8, and an N.sup.+ -diffusion region 13 formed adjacent to the surface of the P-well region in a region where the gate electrode 10 is not formed. A contact window 17 for interconnecting the N.sup.+ -diffusion region 13 and a metal wiring layer (not shown) is formed in a specified portion of the insulating layer 14 on the N.sup.+ -diffusion region 13.
The other MOS transistor is a P-type MOS transistor having a gate oxide 8 formed on the N-epitaxial layer 4, a gate electrode 10 on the gate oxide 8, and a P.sup.+ -diffusion region 12 formed adjacent to the surface of the N-epitaxial layer 4 in a region where the gate electrode 10 is not formed. A contact window 18 for interconnecting the P.sup.+ -diffusion region 12 and a metal wiring layer (not shown) is formed in a specified portion of the insulating layer 14 on the P.sup.+ -diffusion region 12.
When manufacturing the Bi-CMOS of FIG. 27, the emitter diffusion window 15 for the bipolar transistor VBT is formed after the gate oxide 8, and before a poly-Si film (which serves as the gate electrode 10 and emitter electrode 11) are deposited on the gate oxide 8. According to this method, the surface of the P-base region 7 in a region where the emitter region 9 is to be formed is exposed as a result of the formation of the emitter diffusion window 15. This involves a problem in that P-type impurities come out from the exposed P-base region 7 to contaminate the gate oxide 8 before the poly-Si film which serves as the emitter electrode 11 is deposited on the gate oxide 8.
In this method, when the poly-Si film has been deposited on a wafer after the formation of the emitter diffusion window 15, there may remain an oxide film in the interface between the P-base region 7 within the emitter diffusion window 15 and the poly-Si film (i.e., the emitter electrode 11). This oxide film is a native oxide grown by the oxidation of the surface of the P-base region 7 exposed through the emitter window 15, after the formation of the emitter window 15. If the native oxide film is thick, the trouble is caused in that the diffusion of impurities for forming the emitter region 9, from the poly-Si film to the P-base region 7 may not be properly effected. Even if the emitter region 9 is formed, moreover, the presence of the native oxide film may cause an excessive electric resistance to be formed between the emitter region 9 and the emitter electrode 11. Therefore, it is necessary to carry out an etching process in order to remove the native oxide film immediately before the poly-Si film serving as the emitter electrode 11 is formed on the wafer. In the above prior art technique, however, the gate oxide 8 is exposed on the wafer during the etching process, and hence the surface of the gate oxide 8 is also subject to the etching. Where the gate oxide 8 is designed so as to be as thin as 10 nm or so, any decrease in the thickness of the gate oxide 8 causes a substantial degradation in the characteristics of the transistor. If pin holes are formed in the gate oxide 8, serious trouble is caused in that no proper operation of the transistor can be realized.
The insulation between the emitter electrode 11 and the P-base region 7 is provided by the gate oxide 8 formed below the emitter electrode 11. If the thickness of the gate oxide 8 is reduced as a result of the etching process, therefore, the dielectric strength of the interface between the emitter electrode 11 and the P-base region 7 degrades, with the result that a leakage current will flow between the emitter electrode 11 and the P-base region 7.
In the MOS transistors MT, the P.sup.+ -diffusion region 12 and N.sup.+ -diffusion region 13 are formed in self-aligned relation with respect to the gate electrode 10 by the ion implantation technique in which the gate electrode 10 is used as a mask. If both the diffusion regions 12 and 13 are diffused laterally, the diffusion regions 12, 13 will find their way into a region below the gate electrode 10, with the result that the effective channel length of the MOS transistors is reduced. Recent micronized MOS transistors have a gate electrode 10 with a gate length of the order of, for example, 800 nm. Such micronized transistors involve an inherent problem in that the reduced channel length due to the lateral diffusion of the diffusion regions 12 and 13 causes the performance characteristics of the transistors to degrade considerably.
Moreover, in the bipolar transistor of a conventional Bi-CMOS, the contact window 15 is formed in the base diffusion region 7, which is an active base diffusion region, resulting in that the base contact resistance and the base resistance are further increased.